View 24LC00_907161.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? 1996 microchip technology inc. ds21178b-page 1 m 128 bit i 2 c bus serial eeprom device selection table features low power cmos technology - 500 m a typical active current - 250 na typical standby current organized as 16 bytes x 8 bits 2-wire serial interface bus, i 2 c compatible 100 khz (1.8v) and 400 khz (5v) compatibility self-timed write cycle (including auto-erase) 4 ms maximum byte write cycle time 1,000,000 erase/write cycles guaranteed esd protection > 4 kv data retention > 200 years 8l dip, soic, tssop and 5l sot-23 packages temperature ranges available: description the microchip technology inc. 24aa00/24LC00/24c00 (24xx00*) is a 128-bit electrically erasable prom memory organized as 16 x 8 with a 2-wire serial inter- face. low voltage design permits operation down to 1.8 volts for the 24xx00 version, and every version main- tains a maximum standby current of only 1 m a and typ- ical active current of only 500 m a. this device was designed where a small amount of eeprom is needed for the storage of calibration values, id numbers or manufacturing information, etc. the 24xx00 is available in 8-pin pdip, 8-pin soic (150 mil), 8-pin tssop and the 5-pin sot-23 packages. package types block diagram device v cc range temp range 24aa00 1.8 - 6.0 c,i 24LC00 2.5 - 6.0 c,i 24c00 4.5 - 5.5 c,i,e - commercial (c): 0 c to +70 c - industrial (i): -40 c to +85 c - automotive (e) -40 c to +125 c 24xx00 1 2 3 4 8 7 6 5 15 4 3 24xx00 24xx00 8-pin pdip/soic 8-pin tssop 5-pin sot-23 nc nc nc vss v cc nc scl sda nc nc nc v ss v cc nc scl sda scl v ss sda v cc nc 1 2 3 4 8 7 6 5 2 hv generator eeprom array ydec xdec sense amp r/w control memory control logic i/o control logic sda scl v cc v ss 24aa00/24LC00/24c00 *24xx00 is used in this document as a generic part number for the 24aa00/24LC00/24c00 devices. i 2 c is a trademark of philips corporation.
24xx00 ds21178b -page 2 ? 1996 microchip technology inc. 1.0 electrical chara cteristics 1.1 maxim um ratings* v cc ................................................................................... 7.0v all inputs and outputs w .r .t. v ss ................ -0.6v to v cc +1.0v stor age temper ature ..................................... -65?c to +150?c ambient temp . with po w er applied ................. -65?c to +125?c solder ing temper ature of leads (10 seconds) ............. +300?c esd protection on all pins ................................................ 4 kv *notice: stresses abo v e those listed under ?axim um r atings ma y cause per manent damage to the de vice . this is a stress r ating only and functional oper ation of the de vice at those or an y other conditions abo v e those indicated in the oper ational listings of this speci cation is not implied. exposure to maxim um r ating conditions f or e xtended per i- ods ma y aff ect de vice reliability . t able 1-1 pin function t able figure 1-1: b us timing d a t a name function v ss sd a scl v cc nc ground ser ial data ser ial cloc k +1.8v to 6.0v (24aa00) +2.5v to 6.0v (24LC00) +4.5v to 5.5v (24c00) no inter nal connection t able 1-2 dc characteristics all p ar ameters apply across the recom- mended oper ating r anges unless other- wise noted commercial (c): t amb = 0?c to +70?c , v cc = 1.8v to 6.0v industr ial (i) : t amb = -40?c to +85?c , v cc = 1.8v to 6.0v a utomotiv e (e) t amb = -40?c to +125?c , v cc = 4.5v to 5.5v p arameter symbol min. max. units conditions scl and sd a pins: high le v el input v oltage v ih 0.7 v cc v (note) lo w le v el input v oltage v il 0.3 v cc v (note) hysteresis of schmitt tr igger inputs v hys .05 v cc v vcc 3 2.5v (note) lo w le v el output v oltage v ol .40 v i ol = 3.0 ma, v cc = 4.5v i ol = 2.1 ma, v cc = 2.5v input leakage current i li -10 10 m a v in = v cc or v ss output leakage current i lo -10 10 m a v out = v cc or v ss pin capacitance (all inputs/outputs) c in , c out 10 pf v cc = 5.0v (note) t amb = 25?c , f = 1 mhz oper ating current i cc wr ite 2 ma v cc = 5.5v , scl = 400 khz i cc read 1 ma v cc = 5.5v , scl = 400 khz standb y current i ccs 1 m a v cc = 5.5v , sd a = scl = v cc note: this par ameter is per iodically sampled and not 100% tested. t f t high t r t su : sta t low t hd : dat t su : dat t su : sto t buf t aa t sp scl sd a in sd a out t hd : sta
24xx00 ? 1996 microchip technology inc. ds21178b -page 3 t able 1-3 a c characteristics all p ar ameters apply across all recommended oper ating r anges unless otherwise noted commercial (c): t amb = 0?c to +70?c , v cc = 1.8v to 6.0v industr ial (i) : t amb = -40?c to +85?c , v cc = 1.8v to 6.0v a utomotiv e (e): t amb = -40?c to +125?c , v cc = 4.5v to 5.5v p arameter symbol min max units conditions cloc k frequency f clk 100 100 400 khz 4.5v vcc 5.5v (e t emp r ange) 1.8v vcc 4.5v 4.5v vcc 6.0v cloc k high time t high 4000 4000 600 ns 4.5v vcc 5.5v (e t emp r ange) 1.8v vcc 4.5v 4.5v vcc 6.0v cloc k lo w time t low 4700 4700 1300 ns 4.5v vcc 5.5v (e t emp r ange) 1.8v vcc 4.5v 4.5v vcc 6.0v sd a and scl r ise time ( note 1 ) t r 1000 1000 300 ns 4.5v vcc 5.5v (e t emp r ange) 1.8v vcc 4.5v 4.5v vcc 6.0v sd a and scl f all time t f 300 ns ( note 1 ) st ar t condition hold time t hd : sta 4000 4000 600 ns 4.5v vcc 5.5v (e t emp r ange) 1.8v vcc 4.5v 4.5v vcc 6.0v st ar t condition setup time t su : sta 4700 4700 600 ns 4.5v vcc 5.5v (e t emp r ange) 1.8v vcc 4.5v 4.5v vcc 6.0v data input hold time t hd : dat 0 ns ( note 2 ) data input setup time t su : dat 250 250 100 ns 4.5v vcc 5.5v (e t emp r ange) 1.8v vcc 4.5v 4.5v vcc 6.0v st op condition setup time t su : sto 4000 4000 600 ns 4.5v vcc 5.5v (e t emp r ange) 1.8v vcc 4.5v 4.5v vcc 6.0v output v alid from cloc k ( note 2 ) t aa 3500 3500 900 ns 4.5v vcc 5.5v (e t emp r ange) 1.8v vcc 4.5v 4.5v vcc 6.0v bus free time: time the b us m ust be free bef ore a ne w tr ansmission can star t t buf 4700 4700 1300 ns 4.5v vcc 5.5v (e t emp r ange) 1.8v vcc 4.5v 4.5v vcc 6.0v output f all time from v ih minim um to v il maxim um t of 20+0.1 cb 250 ns ( note 1 ), cb 100 pf input lter spik e suppression (sd a and scl pins) t sp 50 ns ( notes 1 , 3 ) wr ite cycle time t wc 4 ms endur ance 1m cycles 25 c , v cc = 5.0v , bloc k mode ( note 4 ) note 1: not 100% tested. cb = total capacitance of one b us line in pf . 2: as a tr ansmitter , the de vice m ust pro vide an inter nal minim um dela y time to br idge the unde ned region (minim um 300 ns) of the f alling edge of scl to a v oid unintended gener ation of st ar t or st op conditions . 3: the combined t sp and v hys speci cations are due to ne w schmitt tr igger inputs which pro vide impro v ed noise spik e suppression. this eliminates the need f or a ti speci cation f or standard oper ation. 4: this par ameter is not tested b ut guar anteed b y char acter ization. f or endur ance estimates in a speci c appli- cation, please consult the t otal endur ance model which can be obtained on microchip s bbs or w ebsite .
24xx00 ds21178b -page 4 ? 1996 microchip technology inc. 2.0 pin descriptions 2.1 sd a serial data this is a bi-directional pin used to tr ansf er addresses and data into and data out of the de vice . it is an open dr ain ter minal, theref ore the sd a b us requires a pull-up resistor to v cc (typical 10 k w f or 100 khz, 2 k w f or 400 khz). f or nor mal data tr ansf er sd a is allo w ed to change only dur ing scl lo w . changes dur ing scl high are reser v ed f or indicating the st ar t and st op conditions . 2.2 scl serial cloc k this input is used to synchroniz e the data tr ansf er from and to the de vice . 2.3 noise pr otection the scl and sd a inputs ha v e schmitt tr igger and lter circuits which suppress noise spik es to assure proper de vice oper ation e v en on a noisy b us . 3.0 functional description the 24xx00 suppor ts a bi-directional 2-wire b us and data tr ansmission protocol. a de vice that sends data onto the b us is de ned as a tr ansmitter , and a de vice receiving data as a receiv er . the b us has to be con- trolled b y a master de vice which gener ates the ser ial cloc k (scl), controls the b us access , and gener ates the st ar t and st op conditions , while the 24xx00 w or ks as sla v e . both master and sla v e can oper ate as tr ansmitter or receiv er , b ut the master de vice deter- mines which mode is activ ated. 4.0 b us chara cteristics the f ollo wing b us pr otocol has been de ned: data tr ansf er ma y be initiated only when the b us is not b usy . dur ing data tr ansf er , the data line m ust remain stab le whene v er the cloc k line is high. changes in the data line while the cloc k line is high will be inter preted as a st ar t or st op condition. accordingly , the f ollo wing b us conditions ha v e been de ned ( figure 4-1 ). 4.1 bus not busy (a) both data and cloc k lines remain high. 4.2 star t data t ransf er (b) a high to lo w tr ansition of the sd a line while the cloc k (scl) is high deter mines a st ar t condition. all commands m ust be preceded b y a st ar t condition. 0.1 stop data t ransf er (c) a lo w to high tr ansition of the sd a line while the cloc k (scl) is high deter mines a st op condition. all oper ations m ust be ended with a st op condition. 4.3 data v alid (d) the state of the data line represents v alid data when, after a st ar t condition, the data line is stab le f or the dur ation of the high per iod of the cloc k signal. the data on the line m ust be changed dur ing the lo w per iod of the cloc k signal. there is one bit of data per cloc k pulse . each data tr ansf er is initiated with a st ar t condition and ter minated with a st op condition. the n umber of the data b ytes tr ansf erred betw een the st ar t and st op conditions is deter mined b y the master de vice and is theoretically unlimited. 4.4 ac kno wledg e each receiving de vice , when addressed, is ob liged to gener ate an ac kno wledge after the reception of each b yte . the master de vice m ust gener ate an e xtr a cloc k pulse which is associated with this ac kno wledge bit. the de vice that ac kno wledges has to pull do wn the sd a line dur ing the ac kno wledge cloc k pulse in such a w a y that the sd a line is stab le lo w dur ing the high per iod of the ac kno wledge related cloc k pulse . of course , setup and hold times m ust be tak en into account. a master m ust signal an end of data to the sla v e b y not gener ating an ac kno wledge bit on the last b yte that has been cloc k ed out of the sla v e . in this case , the sla v e m ust lea v e the data line high to enab le the master to gener ate the st op condition ( figure 4-2 ). note: the 24xx00 does not gener ate an y ac kno wledge bits if an inter nal prog r am- ming cycle is in prog ress .
24xx00 ? 1996 microchip technology inc. ds21178b -page 5 figure 4-1: d a t a transfer seq uence on the serial b us figure 4-2: ac kno wledg e timing 5.0 de vice ad dressing after gener ating a st ar t condition, the b us master tr ansmits a control b yte consisting of a sla v e address and a read/ wr ite bit that indicates what type of oper a- tion is to be perf or med. the sla v e address f or the 24xx00 consists of a 4-bit de vice code (1010) f ollo w ed b y three don't care bits . the last bit of the control b yte deter mines the oper ation to be perf or med. when set to a one a read oper ation is selected, and when set to a z ero a wr ite oper ation is selected. ( figure 5-1 ). the 24xx00 monitors the b us f or its corresponding sla v e address all the time . it gener- ates an ac kno wledge bit if the sla v e address w as tr ue and it is not in a prog r amming mode . figure 5-1: contr ol byte f ormat (a) (b) (c) (d) (a) (c) scl sd a st ar t condition address or a ckno wledge v alid d a t a allo wed t o change st op condition scl 9 8 7 6 5 4 3 2 1 1 2 3 t r ansmitter m ust release the sd a line at this point allo wing the receiv er to pull the sd a line lo w to ac kno wledge the pre vious eight bits of data. receiv er m ust release the sd a line at this point so the t r ansmitter can contin ue sending data. data from tr ansmitter data from tr ansmitter sd a ac kno wledge bit 1 0 1 0 x x x s a ck r/ w de vice select bits don? care bits sla v e address ac kno wledge bit star t bit read/ wr ite bit
24xx00 ds21178b -page 6 ? 1996 microchip technology inc. 6.0 write opera tions 6.1 byte write f ollo wing the star t signal from the master , the de vice code (4 bits), the don't care bits (3 bits), and the r/ w bit (which is a logic lo w) are placed onto the b us b y the master tr ansmitter . this indicates to the addressed sla v e receiv er that a b yte with a w ord address will f ollo w after it has gener ated an ac kno wledge bit dur ing the ninth cloc k cycle . theref ore , the ne xt b yte tr ansmitted b y the master is the w ord address and will be wr itten into the address pointer of the 24xx00 . only the lo w er f our address bits are used b y the de vice , and the upper f our bits are don? cares . the 24xx00 will ac kno wledge the address b yte and the master de vice will then tr ans- mit the data w ord to be wr itten into the addressed mem- or y location. the 24xx00 ac kno wledges again and the master gener ates a stop condition. this initiates the inter nal wr ite cycle , and dur ing this time the 24xx00 will not gener ate ac kno wledge signals ( figure 7-2 ). after a b yte wr ite command, the inter nal address counter will not be incremented and will point to the same address location that w as just wr itten. if a stop bit is tr ansmitted to the de vice at an y point in the wr ite command sequence bef ore the entire sequence is complete , then the command will abor t and no data will be wr itten. if more than 8 data bits are tr ansmitted bef ore the stop bit is sent, then the de vice will clear the pre viously loaded b yte and begin loading the data b uff er again. if more than one data b yte is tr ansmitted to the de vice and a stop bit is sent bef ore a full eight data bits ha v e been tr ansmitted, then the wr ite command will abor t and no data will be wr itten. the 24xx00 emplo ys a v cc thresh- old detector circuit which disab les the inter nal er ase/ wr ite logic if the v cc is belo w 1.5v (24aa00 and 24LC00) or 3.8v (24c00) at nominal conditions . 7.0 a ckno wledge polling since the de vice will not ac kno wledge dur ing a wr ite cycle , this can be used to deter mine when the cycle is complete (this f eature can be used to maximiz e b us throughput). once the stop condition f or a wr ite com- mand has been issued from the master , the de vice ini- tiates the inter nally timed wr ite cycle . a ck polling can be initiated immediately . this in v olv es the master send- ing a star t condition f ollo w ed b y the control b yte f or a wr ite command (r/ w = 0). if the de vice is still b usy with the wr ite cycle , then no a ck will be retur ned. if no a ck is retur ned, then the star t bit and control b yte m ust be re-sent. if the cycle is complete , then the de vice will retur n the a ck and the master can then proceed with the ne xt read or wr ite command. see figure 7-1 f or o w diag r am. figure 7-1: a ckno wledge polling flo w figure 7-2: byte write send wr ite command send stop condition to initiate wr ite cycle send star t send control byte with r/w = 0 did de vice ac kno wledge (a ck = 0)? ne xt oper ation no yes s p b us a ctivity master sd a line b us a ctivity s t a r t s t o p contr ol byte w ord address d a t a a c k a c k a c k 1 0 x 1 0 x x x x = don? care bit x x x 0
24xx00 ? 1996 microchip technology inc. ds21178b -page 7 8.0 read opera tions read oper ations are initiated in the same w a y as wr ite oper ations with the e xception that the r/ w bit of the sla v e address is set to one . there are three basic types of read oper ations: current address read, r andom read, and sequential read. 8.1 current ad dress read the 24xx00 contains an address counter that maintains the address of the last w ord accessed, inter nally incre- mented b y one . theref ore , if the pre vious read access w as to address n, the ne xt current address read oper a- tion w ould access data from address n + 1. upon receipt of the sla v e address with the r/ w bit set to one , the de vice issues an ac kno wledge and tr ansmits the eight bit data w ord. the master will not ac kno wledge the tr ansf er b ut does gener ate a stop condition and the de vice discontin ues tr ansmission ( figure 8-1 ). 8.2 random read random read oper ations allo w the master to access an y memor y location in a r andom manner . t o perf or m this type of read oper ation, rst the w ord address m ust be set. this is done b y sending the w ord address to the de vice as par t of a wr ite oper ation. after the w ord address is sent, the master gener ates a star t condition f ollo wing the ac kno wledge . this ter minates the wr ite oper ation, b ut not bef ore the inter nal address pointer is set. then the master issues the control b yte again b ut with the r/ w bit set to a one . the 24xx00 will then issue an ac kno wledge and tr ansmits the eight bit data w ord. the master will not ac kno wledge the tr ansf er b ut does gener ate a stop condition and the de vice discontin ues tr ansmission ( figure 8-2 ). after this command, the inter nal address counter will point to the address loca- tion f ollo wing the one that w as just read. 8.3 sequential read sequential reads are initiated in the same w a y as a r an- dom read e xcept that after the de vice tr ansmits the rst data b yte , the master issues an ac kno wledge as opposed to a stop condition in a r andom read. this directs the de vice to tr ansmit the ne xt sequentially addressed 8-bit w ord ( figure 8-3 ). t o pro vide sequential reads the 24xx00 contains an inter nal address pointer which is incremented b y one at the completion of each read oper ation. this address pointer allo ws the entire memor y contents to be ser ially read dur ing one oper ation. figure 8-1: current address read figure 8-2: random read figure 8-3: seq uential read b us a ctivity master sd a line b us a ctivity p s s t o p contr ol byte s t a r t d a t a a c k n o a c k 1 1 0 0 x x x 1 x = don? care bit p b us a ctivity master sd a line b us a ctivity s t a r t s t o p contr ol byte a c k w ord address (n) contr ol byte s t a r t d a t a (n) a c k a c k n o a c k x x x x s 1 1 0 0 x x x 0 s 1 1 0 0 x x x 1 x = don? care bit p b us a ctivity master sd a line b us a ctivity s t o p contr ol byte a c k n o a c k d a t a n d a t a n + 1 d a t a n + 2 d a t a n + x a c k a c k a c k
24xx00 ds21178b -page 8 ? 1996 microchip technology inc. notes:
24xx00 ? 1996 microchip technology inc. ds21178b -page 9 notes:
24xx00 ds21178b -page 10 ? 1996 microchip technology inc. notes:
24xx00 ? 1996 microchip technology inc. ds21178b -page 11 24xx00 pr oduct identification system t o order or obtain inf or mation, e .g., on pr icing or deliv er y , ref er to the f actor y or the listed sales of ce . sales and suppor t p ac ka g e: p = plastic dip (300 mil body), 8-lead sn = plastic soic (150 mil body) st = tssop , 8-lead o t = so t -23, 5-lead t emperature blank = 0 ? c to +70 ? c rang e: i = ?0 ? c to +85 ? c e = ?0 ? c to +125 ? c de vice: 24aa00 128 bit 1.8v i 2 c ser ial eepr om 24aa00t 128 bit 1.8v i 2 c ser ial eepr om (t ape and reel) 24LC00 128 bit 2.5v i 2 c ser ial eepr om 24LC00t 128 bit 2.5v i 2 c ser ial eepr om (t ape and reel) 24c00 128 bit 5.0v i 2 c ser ial eepr om 24c00t 128 bit 5.0v i 2 c ser ial eepr om (t ape and reel) 24xx00 /p data sheets products suppor ted b y a preliminar y data sheet ma y ha v e an err ata sheet descr ibing minor oper ational diff erences and recom- mended w or karounds . t o deter mine if an err ata sheet e xists f or a par ticular de vice , please contact one of the f ollo wing: 1. y our local microchip sales of ce (see last page). 2. the microchip cor por ate liter ature center u .s . f ax: (602) 786-7277. 3. the microchip s bulletin board, via y our local compuser v e n umber (compuser v e membership no t required). please specify which de vice , re vision of silicon and data sheet (include liter ature #) y ou are using. de velopment t ools f or the latest v ersion inf or mation and upg r ade kits f or microchip de v elopment t ools , please call 1-800-755-2345 or 1-602-786-7302. the latest v ersion of de v elopment t ools softw are can be do wnloaded from either our bulletin board or w or ldwide w eb site .
in f o r mation contained in this publication regarding d e vice applications and the like is intended f or suggestion only and may be superseded by updates . no representation or w arranty is gi v en and no liability is assumed by microchi p t echnology inco r porated with respect to the accu r acy or use of such in f o r mation, or inf r ingement of patents or other intellectual prope r ty r ights a r ising from such use or otherwis e . use of microchip ? s products as c r itical components in li f e suppo r t systems is not autho r i z ed e xcept with e xpress w r itten appro v al b y microchi p . no licenses are con v ey ed, implicitly or otherwise, under any intellectual prope r ty r ight s . the microchip logo and name are registered t r adema r ks of microchi p t echnology inc . in the u . s .a . and other count r ie s . all r ights rese r v ed . all other tradema r ks mentioned herein are the prope r ty of their respective companies. ds 21178b-page 12 ? 1997 microchip technology inc. americas corporate of?e microchip t echnolog y inc. 235 5 w est chandler blvd. chandle r , az 85224-6199 t el : 602-786-7200 f ax : 602-786-7277 technical support: 602 786-7627 web: http://ww w .microchi p .com atlanta microchip t echnolog y inc. 500 sugar mill road, suite 200b atlanta, ga 30350 t el : 770-640-0034 f ax : 770-640-0307 boston microchip t echnolog y inc. 5 mount r o y al a v enue ma r lborough, ma 01752 t el : 508-480-9990 f ax : 508-480-8575 chicago microchip t echnolog y inc. 333 pierce road, suite 180 itasca, il 60143 t el : 630-285-0071 f ax : 630-285-0075 dallas microchip t echnolog y inc. 14651 dallas p a r k w a y , suite 816 dalla s , tx 75240-8809 t el : 972-991-7177 f ax : 972-991-8588 d a yton microchip t echnolog y inc. t wo prestige plac e , suite 150 miamis b urg, oh 45342 t el : 937-291-1654 f ax : 937-291-9175 los angeles microchip t echnolog y inc. 1820 1 v on ka r man, suite 1090 i r vin e , ca 92612 t el : 714-263-1888 f ax : 714-263-1338 n e w y ork microchip t echnolog y inc. 150 motor p a r k w a y , suite 416 hauppaug e , ny 11788 t el : 516-273-5305 f ax : 516-273-5335 san jose microchip t echnolog y inc. 2107 no r th first street, suite 590 san jos e , ca 95131 t el : 408-436-7950 f ax : 408-436-7955 t o r onto microchip t echnolog y inc. 5925 ai r po r t road, suite 200 mississauga, onta r io l4v 1w1, canada t el : 905-405-6279 f ax : 905-405-6253 asia/ p a cific hong k ong microchip asia p aci? r m 3801 b , t o wer t wo metroplaza 223 hing f ong road k w ai f ong, n. t ., hong k ong t el : 852-2-401-1200 f ax : 852-2-401-3431 india microchip t echnolog y inc. india liaison of?e n o . 6, legac y , co n v ent road bangalore 560 025, india t el : 91-80-229-4036 f ax : 91-80-559-9840 k orea microchip t echnolog y k orea 168-1 , y oungbo bldg . 3 floor samsung-dong, kangnam- k u seoul, k orea t el : 82-2-554-7200 f ax : 82-2-558-5934 shanghai microchip t echnology rm 406 shanghai golden b r idge bldg. 207 7 y an?n roa d w est, hong qiao dist r ict shanghai, prc 200335 t el : 86-21-6275-5700 f ax : 86 21-6275-5060 singapore microchip t echnology t ai w an singapore branch 200 middle road #10-03 p r ime centre singapore 188980 t el : 65-334-8870 f ax : 65-334-8850 t aiwan , r. o .c microchip t echnology t ai w an 10f-1c 207 t ung hua no r th road t aipei, t ai w an , r o c t el : 886 2-717-7175 f ax : 886-2-545-0139 eu r ope united kingdom a r i z ona microchi p t echnology ltd. unit 6 , the cou r t y ard mead o w bank, fu r long road bou r ne end, bu c kinghamshire sl8 5aj t el : 44-1628-851077 f ax : 44-1628-850259 france a r i z ona microchi p t echnology sarl zone indust r ielle de la bonde 2 rue du buisson aux f raises 91300 mass y , f rance t el : 33-1-69-53-63-20 f ax : 33-1-69-30-90-79 germa n y a r i z ona microchi p t echnology gmbh gust a v-heinemann-ring 125 d-81739 m?chen, ge r ma n y t el : 49-89-627-144 0 f ax : 49-89-627-144-44 ita l y a r i z ona microchi p t echnology srl centro direzionale colleoni p alaz z o t au r us 1 v . le colleoni 1 20041 agrate b r ianza milan, italy t el : 39-39-6899939 f ax : 39-39-6899883 j a p a n microchi p t echnology intl . inc. ben e x s-1 6f 3-18-20, shi n y o k ohama k ohoku- k u, y o k ohama-shi kanag a w a 222 j apan t el : 81-45-471- 6166 f ax : 81-45-471-6122 7/29/97 p r inted on recycled pape r . all r ights rese r v ed . ?997, microchi p t echnology inco r porated, usa . 8/97 m w orldwide s ales & s ervice

▲Up To Search▲

Price & Availability of 24LC00

	To Download 24LC00 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .